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--- en:multiasm:piot:chapter_4_5 [2024/09/27 20:55] – pczekalski
+++ en:multiasm:piot:chapter_4_5 [2025/05/31 07:20] (current) – marcin
@@ Line 1: / Line 1: @@
 ====== Addressing Modes ======
+Addressing modes define how the processor accesses data. There are 15 different addressing modes, such as: Direct Addressing, Indirect Addressing, Indirect with Displacement, Immediate Addressing, Register Addressing, Relative Addressing, Indirect I/O Addressing, and Stack Addressing.
+Details:
+**1. Direct Single Register Addressing**
+{{:en:multiasm:piot:adr01.png?400|}}
+The operand is contained in the destination register (Rd).
+**2. Direct Register Addressing, Two Registers**
+{{:en:multiasm:piot:adr02.png?400|}}
+Operands are contained in the source register (Rr) and destination register (Rd). The result is stored in the destination register (Rd).
+**3. I/O Direct Addressing**
+{{:en:multiasm:piot:adr03.png?400|}}
+Operand address A is contained in the instruction word. Rr/Rd specifies the destination or source register.
+**4. Data Direct Addressing**
+{{:en:multiasm:piot:adr04.png?400|}}
+A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or source register. The LDS instruction uses the RAMPD register to access memory above 64 KB.
+**5. Data Indirect Addressing**
+{{:en:multiasm:piot:adr05.png?400|}}
+The operand address is the contents of the X-, Y-, or Z-pointer. Data Indirect Addressing is called Register Indirect Addressing in AVR devices without SRAM.
+**6. Data Indirect Addressing with Pre-decrement**
+{{:en:multiasm:piot:adr06.png?400|}}
+The X,- Y-, or the Z-pointer is decremented before the operation. The operand address is the decremented contents of the X-, Y-, or the Z-pointer.
+**7. Data Indirect Addressing with Post-increment**
+{{:en:multiasm:piot:adr07.png?400|}}
+The X-, Y-, or the Z-pointer is incremented after the operation. The operand address is the content of the X-, Y-, or the Z-pointer before incrementing.
+**8. Data Indirect with Displacement**
+{{:en:multiasm:piot:adr08.png?400|}}
+The operand address is the result of the q displacement contained in the instruction word added to the Y- or Z-pointer. Rd/Rr specify the destination or source register.
+**9. Program Memory Constant Addressing**
+{{:en:multiasm:piot:adr09.png?400|}}
+Constant byte address is specified by the Z-pointer contents. The 15 MSbs select the word address. For LPM, the LSb selects the low byte if cleared (LSb == 0) or high byte if set (LSb == 1). For SPM, the LSb should be cleared. If ELPM is used, the RAMPZ Register is used to extend the Z-register.
+**10. Program Memory Addressing with Post-increment**
+Constant byte address is specified by the Z-pointer contents. The 15 MSbs select word address. The LSb selects low byte if cleared (LSb == 0) or high byte if set (LSb == 1). If ELPM Z+ is used, the RAMPZ Register is used to extend the Z-register.
+**11. Store Program Memory**
+{{:en:multiasm:piot:adr11.png?400|}}
+The Z-pointer is incremented by 2 after the operation. Constant byte address is specified by the Z-pointer contents before incrementing. The 15 MSbs select word address and the LSb should be left cleared.
+**12. Direct Program Memory Addressing**
+{{:en:multiasm:piot:adr12.png?400|}}
+Program execution continues at the address immediate in the instruction word.
+**13. Indirect Program Memory Addressing**
+{{:en:multiasm:piot:adr13.png?400|}}
+Program execution continues at the address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register).
+**14. Extended Indirect Program Memory Addressing**
+{{:en:multiasm:piot:adr14.png?400|}}
+Program execution continues at the address contained by the Z-register and the EIND-register (i.e., the PC is loaded with the contents of the EIND and Z-register).
+**15. Relative Program Memory Addressing**
+{{:en:multiasm:piot:adr15.png?400|}}
+Program execution continues at the address PC + k + 1. The relative address k is from -2048 to 2047.

en/multiasm/piot/chapter_4_5.1727470516.txt.gz · Last modified: 2024/09/27 20:55 by pczekalski