Hello !
Trace: • Instruction Set • Procedures and Functions Call Standards • Overall View on Computer Architecture: Processor, Memory, IO, Buses • CAN HomeLab kit • Processor Taxonomies, SISD, SIMD, MIMD • Addressing Modes • IoT Attack Vectors

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
en:multiasm:cs:chapter_3_1 [2025/11/28 08:41] – [Buses] ktokarzen:multiasm:cs:chapter_3_1 [2025/11/28 09:02] (current) – [Buses] ktokarz
Line 30: Line 30:
 The processor, memory and peripherals exchange information using interconnections called buses. Although you can find in the literature and on the internet a variety of bus types and their names, at the very lowest level, there are three buses connecting the processor, memory, and peripherals.  The processor, memory and peripherals exchange information using interconnections called buses. Although you can find in the literature and on the internet a variety of bus types and their names, at the very lowest level, there are three buses connecting the processor, memory, and peripherals. 
  
-**Address bus** delivers the address generated by the processor to memory or peripherals. This address specifies the single memory cell or peripheral register that the processor wants to access. The address bus is used not only to address the data which the processor wants to transmit to or from memory or a peripheral. It also addresses the instruction that the processor fetches and later executes. Instructions are also stored in the memory. The address bus is one-directional. The address is generated by the processor and delivered to other units. +**Address bus** delivers the address generated by the processor to memory or peripherals. This address specifies the single memory cell or peripheral register that the processor wants to access. The address bus is used not only to address the data which the processor wants to transmit to or from memory or a peripheral. Instructions are also stored in memory, so the address bus also selects the instruction that the processor fetches and later executes. The address bus is one-directional. The address is generated by the processor and delivered to other units. 
 <note info> If there is a DMA controller in the computer, in some circumstances, it can also generate an address instead of the processor. Refer to the chapter with the DMA description. </note> <note info> If there is a DMA controller in the computer, in some circumstances, it can also generate an address instead of the processor. Refer to the chapter with the DMA description. </note>
 The number of lines in the address bus is fixed for the processor and determines the size of the addressing space the processor can access. For example, if the address bus of some processor has 16 lines, it can generate up to 16^2 = 65536 different addresses. The number of lines in the address bus is fixed for the processor and determines the size of the addressing space the processor can access. For example, if the address bus of some processor has 16 lines, it can generate up to 16^2 = 65536 different addresses.
en/multiasm/cs/chapter_3_1.1764319291.txt.gz · Last modified: 2025/11/28 08:41 by ktokarz
CC Attribution-Share Alike 4.0 International
www.chimeric.de Valid CSS Driven by DokuWiki do yourself a favour and use a real browser - get firefox!! Recent changes RSS feed Valid XHTML 1.0