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| en:multiasm:cs:chapter_3_1 [2025/11/28 08:14] – [Processor] ktokarz | en:multiasm:cs:chapter_3_1 [2025/11/28 09:02] (current) – [Buses] ktokarz | ||
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| Memory is the element of the computer that stores data and programs. It is visible to the processor as a sequence of data words, where every word has its own address. Addressing allows the processor to access simple and complex variables and to read the instructions for execution. Although intuitively, | Memory is the element of the computer that stores data and programs. It is visible to the processor as a sequence of data words, where every word has its own address. Addressing allows the processor to access simple and complex variables and to read the instructions for execution. Although intuitively, | ||
| <note info> The byte is historically assumed as 8 bits of information and used as the base unit to express the size of data in the world of computers. </ | <note info> The byte is historically assumed as 8 bits of information and used as the base unit to express the size of data in the world of computers. </ | ||
| - | The size of the memory installed on the computer does not have to correspond to the size of the address space – the maximal size of the memory which is addressable by the processor. In modern machines, it would be impossible or hardly achievable. For example, for x64 architecture, | + | The size of the memory installed on the computer does not have to correspond to the size of the address space, the maximal size of the memory which is addressable by the processor. In modern machines, it would be impossible or hardly achievable. For example, for x64 architecture, |
| <note info> To learn more about paging please refer to https:// | <note info> To learn more about paging please refer to https:// | ||
| ===== Peripherals ===== | ===== Peripherals ===== | ||
| - | Called also input-output (I/O) devices. There is a variety of units belonging to this group. It includes timers, communication ports, general-purpose inputs and outputs, displays, network controllers, | + | Called also input-output (I/O) devices. There is a variety of units belonging to this group. It includes timers, communication ports, general-purpose inputs and outputs, displays, network controllers, |
| ===== Buses ===== | ===== Buses ===== | ||
| - | Processor, memory and peripherals exchange information using interconnections called buses. Although you can find in the literature and internet a variety of kinds of buses and their names, | + | The processor, memory and peripherals exchange information using interconnections called buses. Although you can find in the literature and on the internet a variety of bus types and their names, |
| - | **Address bus** delivers the address generated by the processor to memory or peripherals. This address specifies the one, and only one memory cell or peripheral register that the processor wants to access. The address bus is used not only to address the data which the processor wants to transmit to or from memory or peripheral. | + | **Address bus** delivers the address generated by the processor to memory or peripherals. This address specifies the single |
| - | <note info> If there is the DMA controller in the computer, in some circumstances it also can generate an address instead of the processor. Refer to the chapter with the DMA description. </ | + | <note info> If there is a DMA controller in the computer, in some circumstances, it can also generate an address instead of the processor. Refer to the chapter with the DMA description. </ |
| The number of lines in the address bus is fixed for the processor and determines the size of the addressing space the processor can access. For example, if the address bus of some processor has 16 lines, it can generate up to 16^2 = 65536 different addresses. | The number of lines in the address bus is fixed for the processor and determines the size of the addressing space the processor can access. For example, if the address bus of some processor has 16 lines, it can generate up to 16^2 = 65536 different addresses. | ||
| - | **Data bus** is used to exchange data between processor and memory or peripherals. The processor can read the data from memory or peripherals or write the data to these units previously sending their address with the address bus. As data can be read or written the data bus is bi-directional. | + | **Data bus** is used to exchange data between |
| - | <note info> In the systems with a DMA controller the data bus is utilised to exchange | + | <note info> In the systems with a DMA controller, the data bus is utilised to exchange data between memory and peripherals directly. Refer to the chapter with the DMA description. </ |
| The number of bits of the data bus usually corresponds to the class of the processor. It means that an 8-bit class processor has 8 lines of the data bus. | The number of bits of the data bus usually corresponds to the class of the processor. It means that an 8-bit class processor has 8 lines of the data bus. | ||
| - | **Control bus** is formed by lines mainly used for synchronisation between the elements of the computer. In the minimal implementation, | + | **Control bus** is formed by lines mainly used for synchronisation between the elements of the computer. In the minimal implementation, |
| The control bus can also include other signals specific to the system, e.g. interrupt signals, DMA control lines, clock pulses, signals distinguishing the memory and peripheral access, signals activating chosen modules and others. | The control bus can also include other signals specific to the system, e.g. interrupt signals, DMA control lines, clock pulses, signals distinguishing the memory and peripheral access, signals activating chosen modules and others. | ||
