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--- en:multiasm:papc:chapter_6_6 [2025/08/01 06:37] – [Scale Index Base byte] ktokarz
+++ en:multiasm:papc:chapter_6_6 [2025/08/01 06:59] (current) – [Scale Index Base byte] ktokarz
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 </code>
-Certainly, the presented examples do not exhaust all possible situations. For a more detailed explanation, please refer to the Intel documentation, OSDev wiki((https://wiki.osdev.org/X86-64_Instruction_Encoding#REX_prefix)) or other interesting sources mentioned at the bottom of this section.
+Certainly, the presented examples do not exhaust all possible situations. For a more detailed explanation, please refer to the documentation by AMD((https://docs.amd.com/v/u/en-US/40332-PUB_4.08)), Intel((https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html)), OSDev wiki((https://wiki.osdev.org/X86-64)) or other interesting sources mentioned at the bottom of this section.
 =====Displacement=====
 Displacement gives the offset for memory operands. Depending on the addressing mode, it can be the direct memory address or an additional offset added to the contents of the base, index register or both. Displacement can be 1, 2, or 4 bytes long. Some instructions allow using an 8-byte displacement. In these instructions, there is no immediate field.

en/multiasm/papc/chapter_6_6.1754030240.txt.gz · Last modified: 2025/08/01 06:37 by ktokarz