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--- en:multiasm:papc:chapter_6_6 [2025/08/01 06:18] – [Scale Index Base byte] ktokarz
+++ en:multiasm:papc:chapter_6_6 [2025/08/01 06:59] (current) – [Scale Index Base byte] ktokarz
@@ Line 332: / Line 332: @@
                        ;                                   1   0   0   0
+;MOD R/M (second byte) is 0x04 for all instructions:
+                       ;                    MOD R.REG R/M   REG  MOD & R/M
+                       ;                     00 0.000 100   eax  SIB is present
                        ;                        Scale X.Index B.Base  Scale Index Base
-mov rax, [rbx+rcx]     ;0x48, 0x8B, 0x04, 0x0B     00   0.001  0.011     x1   ecx  ebx
+mov rax, [rbx+rcx]     ;0x48, 0x8B, 0x04, 0x0B     00   0.001  0.011     x1   rcx  rbx
-mov rax, [rbx+rcx*2]   ;0x48, 0x8B, 0x04, 0x4B     01   0.001  0.011     x2   ecx  ebx
+mov rax, [rbx+rcx*2]   ;0x48, 0x8B, 0x04, 0x4B     01   0.001  0.011     x2   rcx  rbx
-mov rax, [rbx+rcx*4]   ;0x48, 0x8B, 0x04, 0x8B     10   0.001  0.011     x4   ecx  ebx
+mov rax, [rbx+rcx*4]   ;0x48, 0x8B, 0x04, 0x8B     10   0.001  0.011     x4   rcx  rbx
-mov rax, [rbx+rcx*8]   ;0x48, 0x8B, 0x04, 0xCB     11   0.001  0.011     x8   ecx  ebx
+mov rax, [rbx+rcx*8]   ;0x48, 0x8B, 0x04, 0xCB     11   0.001  0.011     x8   rcx  rbx
 </code>
+If any of the new registers (R8-R15) is used in the instruction, it changes the bits in the REX prefix.
+<code asm>
+                       ;                        Scale X.Index B.Base  Scale Index Base
+mov rax, [r10+rcx]     ;0x49, 0x8B, 0x04, 0x0A     00   0.001  1.010     x1   rcx  r10
+mov rax, [rbx+r11]     ;0x4A, 0x8B, 0x04, 0x1B     00   1.001  0.011     x1   r11  rbx
+mov r12, [rbx+rcx]     ;0x4C, 0x8B, 0x24, 0x0B     10   0.001  0.011     x1   rcx  rbx
+                       ;Last instruction has the MOD R/M REG field extended
+                       ;by the R bit from the REX prefix.
+                       ;                    MOD R.REG R/M   REG  MOD & R/M
+                       ;                     00 1.100 100   r12  SIB is present
+</code>
+Certainly, the presented examples do not exhaust all possible situations. For a more detailed explanation, please refer to the documentation by AMD((https://docs.amd.com/v/u/en-US/40332-PUB_4.08)), Intel((https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html)), OSDev wiki((https://wiki.osdev.org/X86-64)) or other interesting sources mentioned at the bottom of this section.
 =====Displacement=====
 Displacement gives the offset for memory operands. Depending on the addressing mode, it can be the direct memory address or an additional offset added to the contents of the base, index register or both. Displacement can be 1, 2, or 4 bytes long. Some instructions allow using an 8-byte displacement. In these instructions, there is no immediate field.

en/multiasm/papc/chapter_6_6.1754029082.txt.gz · Last modified: 2025/08/01 06:18 by ktokarz