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--- en:multiasm:papc:chapter_6_5 [2025/05/29 07:49] – [Index addressing with scaling] ktokarz
+++ en:multiasm:papc:chapter_6_5 [2025/08/20 09:55] (current) – [Addressing Modes in Instructions] ktokarz
@@ Line 1: / Line 1: @@
 ====== Addressing Modes in Instructions ======
-Addressing mode specifies how the processor reaches the data in the memory. x86 architecture implements immediate, direct and indirect memory addressing. Indirect addressing can use a single or two registers and a constant to calculate the final address. The addressing mode takes the name of the registers used. The 32-bit mode makes the choice of the register for addressing more flexible and enhances addressing with the possibility of scaling: multiplying one register by a small constant. In 64-bit mode, addressing relative to the instruction pointer was added for easy relocation of programs in memory. In this chapter, we will focus on the details of all addressing modes in 16, 32 and 64-bit processors.
+Addressing mode specifies how the processor reaches the data in the memory. The x86 architecture implements immediate, direct and indirect memory addressing. Indirect addressing can use a single or two registers and a constant to calculate the final address. The addressing mode takes the names of the registers used. The 32-bit mode makes the choice of the register for addressing more flexible and enhances addressing with the possibility of scaling: multiplying one register by a small constant. In 64-bit mode, addressing relative to the instruction pointer was added for easy relocation of programs in memory. In this chapter, we will focus on the details of all addressing modes in 16, 32 and 64-bit processors.
 In each addressing mode, we are using the simple examples with the mov instruction. The move instruction copies data from the source operand to the destination operand. The order of the operands in instructions is similar to that of high-level languages. The left operand is the destination, the right operand is the source, as in the following example:
 <code asm>
 mov destination, source
 </code>
+<note>
+Calculating the addresses for control transfer instructions, including jumps and procedure calls, will be described in the section about these instructions.
+</note>
 ===== Immediate addressing =====
 The immediate argument is a constant encoded as part of the instruction. This means that this value is encoded in a code section of the program and can't be modified during program execution.
@@ Line 171: / Line 174: @@
 </figure>
-In x86
+MASM assembler accepts different notations of the base + index + displacement, as shown in the code. In the x86, the order of registers written in the instruction is irrelevant.
+<code asm>
+; copy one byte from the data segment in the memory at the address calculated
+; as the sum of the base (BX) register, the index (SI) register and a displacement to AL
+mov al, [bx] + [si] + table
+mov al, [bx + si] + table
+mov al, [bx] [si] + table
+mov al, table [si] [bx]
+mov al, table [si] + [bx]
+mov al, table [si + bx]
+</code>
+In 32- or 64-bit processors, the first register used in the instruction is the base register, and the second is the index register. While segmentation is enabled, the use of EBP or ESP as a base register determines the segment register choice. The displacement can be placed at any position in the address argument expression. Some examples are shown below.
+<code asm>
+; copy one byte from the data or stack segment in memory at the address calculated
+; as the sum of the base, index and displacement (table) to AL
+mov al, [eax] + [esi] + table   ; data segment
+mov al, table + [ebx] + [edi]   ; data segment
+mov al, table [ecx] [esi]       ; data segment
+mov al, [edx] [edi] + table     ; data segment
+mov al, table + [ebp] + [esi]   ; stack segment
+mov al, [esp] + [edi] + table   ; stack segment
+</code>
@@ Line 204: / Line 229: @@
 </figure>
-The scaled register is assumed as the index, the other one is the base (even if it is used first in the instruction). While segmentation is enabled, the use of EBP or ESP as a base register determines the segment register choice.
+The scaled register is assumed as the index, the other one is the base (even if it is not used first in the instruction). While segmentation is enabled, the use of EBP or ESP as a base register determines the segment register choice.
 <code asm>
 ; copy one byte from the data or stack segment in memory at the address calculated
@@ Line 226: / Line 251: @@
 </figure>
+As in the base indexed mode with scaling without displacement, the scaled register is assumed as the index, and the other one is the base (even if it is not used first in the instruction). While segmentation is enabled, the use of EBP or ESP as a base register determines the segment register choice. The displacement can be placed at any position in the instruction.
+<code asm>
+; copy one byte from the data or stack segment in memory at the address calculated
+; as the sum of the base, scaled index and displacement (table) to AL
+mov al, [eax] + [esi * 2] + table   ; data segment
+mov al, table + [ebx] + [edi * 4]   ; data segment
+mov al, table + [ebp] + [esi * 2]   ; stack segment
+mov al, [esp] + [edi * 4] + table   ; stack segment
+</code>

en/multiasm/papc/chapter_6_5.1748504942.txt.gz · Last modified: 2025/05/29 07:49 by ktokarz