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| en:multiasm:papc:chapter_6_3 [2025/05/09 14:27] – [ZMM registers] ktokarz | en:multiasm:papc:chapter_6_3 [2025/12/19 13:02] (current) – [ZMM registers] ktokarz |
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| </figure> | </figure> |
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| To control the behaviour and to provide information about the status of the SSE unit, the MXCSR register is implemented {{ref>mxcsrreg}}. It is a 32-bit register with bits with their functions similar to the FPU unit's Control Word and Status Word registers concatenated together. | To control the behaviour and to provide information about the status of the SSE unit, the MXCSR register is implemented (figure {{ref>mxcsrreg}}). It is a 32-bit register with bits with their functions similar to the FPU unit's Control Word and Status Word registers concatenated together. |
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| <figure mxcsrreg> | <figure mxcsrreg> |
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| <figure zmmregs> | <figure zmmregs> |
| {{ :en:multiasm:cs:zmm_registers.png?800 |Illustration of the 512-bit ZMM registers}} | {{ :en:multiasm:cs:zmm_registers.png?600 |Illustration of the 512-bit ZMM registers}} |
| <caption>512-bit ZMM registers</caption> | <caption>512-bit ZMM registers</caption> |
| </figure> | </figure> |
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| <figure xyzmmregs> | <figure xyzmmregs> |
| {{ :en:multiasm:cs:xyzmm_register.png?800 |Illustration of the relation between XMM, YMM and ZMM registers}} | {{ :en:multiasm:cs:xyzmm_register.png?600 |Illustration of the relation between XMM, YMM and ZMM registers}} |
| <caption>The relation between XMM, YMM and ZMM registers</caption> | <caption>The relation between XMM, YMM and ZMM registers</caption> |
| </figure> | </figure> |
