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| en:multiasm:papc:chapter_6_2 [2025/04/30 10:57] – [Paging] ktokarz | en:multiasm:papc:chapter_6_2 [2025/04/30 12:14] (current) – [Addressing in x64 processors] ktokarz | ||
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| - | As currently built computers have significantly less physical memory than can be theoretically addressed with a 64-bit linear address, producers decided to limit the usable address space. That's why the 4-level paging mechanism recognises only 48 bits, leaving the upper bits unused. In 5-level paging, 57 bits are recognised. The most significant part of the address should have the value of the highest recognisable bit form the address | + | As currently built computers have significantly less physical memory than can be theoretically addressed with a 64-bit linear address, producers decided to limit the usable address space. That's why the 4-level paging mechanism recognises only 48 bits, leaving the upper bits unused. In 5-level paging, 57 bits are recognised. The most significant part of the address should have the value of the highest recognisable bit from the address. As the most significant bit of the number represents |
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| + | Sign-extended addresses having 48 or 57 recognised bits are known as canonical addresses, while others are non-canonical. It is presented in Fig {{ref> | ||
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| + | <figure canonical> | ||
| + | {{ : | ||
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| + | </ | ||
| ===== Addressing in x64 processors ===== | ===== Addressing in x64 processors ===== | ||
| Because the segmentation wasn't used by operating systems software producers, AMD and Intel decided to abandon segmentation in 64-bit processors. For backwards compatibility, | Because the segmentation wasn't used by operating systems software producers, AMD and Intel decided to abandon segmentation in 64-bit processors. For backwards compatibility, | ||
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| In x64 bit mode, some instructions can use segment registers FS and GS as base registers. Operating systems' | In x64 bit mode, some instructions can use segment registers FS and GS as base registers. Operating systems' | ||
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| - | The 64-bit mode theoretically allows the processor to address a vast memory of 16 exabytes in size. It is expected that such a big memory will not be installed in currently built computers, so the processors limit the available address space. | + | The 64-bit mode theoretically allows the processor to address a vast memory of 16 exabytes in size. It is expected that such a big memory will not be installed in currently built computers, so the processors limit the available address space, not only at the paging level but also physically, having a limited number of address bus lines. |
