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| en:multiasm:papc:chapter_6_2 [2025/04/30 11:59] – [Paging] ktokarz | en:multiasm:papc:chapter_6_2 [2025/04/30 12:14] (current) – [Addressing in x64 processors] ktokarz | ||
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| In x64 bit mode, some instructions can use segment registers FS and GS as base registers. Operating systems' | In x64 bit mode, some instructions can use segment registers FS and GS as base registers. Operating systems' | ||
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| - | The 64-bit mode theoretically allows the processor to address a vast memory of 16 exabytes in size. It is expected that such a big memory will not be installed in currently built computers, so the processors limit the available address space. | + | The 64-bit mode theoretically allows the processor to address a vast memory of 16 exabytes in size. It is expected that such a big memory will not be installed in currently built computers, so the processors limit the available address space, not only at the paging level but also physically, having a limited number of address bus lines. |
