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en:multiasm:papc:chapter_6_10 [2025/10/31 10:06] – [Comparison instructions] ktokarzen:multiasm:papc:chapter_6_10 [2025/10/31 16:28] (current) – [Table] ktokarz
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 </figure> </figure>
  
 +The stack organisation of registers makes it easier to implement math calculations according to the RPN (Reverse Polish Notation), also called postfix notation.
 Further in this section, we'll present the FPU coprocessor's instructions. They can be grouped as: Further in this section, we'll present the FPU coprocessor's instructions. They can be grouped as:
   * data transfer instructions,    * data transfer instructions, 
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 If one of the arguments is NaN, they generate the invalid arithmetic operand exception. To avoid unwanted exceptions, there are unordered versions of comparison instructions. These are **fucom**, **fucomp**, and **fucompp**. Unordered comparison instructions do not operate with memory arguments. Two instructions are implemented to compare integers. The **ficom** and **ficomp** have a single memory argument that can be a word or doubleword, which is compared with the top of the stack. If one of the arguments is NaN, they generate the invalid arithmetic operand exception. To avoid unwanted exceptions, there are unordered versions of comparison instructions. These are **fucom**, **fucomp**, and **fucompp**. Unordered comparison instructions do not operate with memory arguments. Two instructions are implemented to compare integers. The **ficom** and **ficomp** have a single memory argument that can be a word or doubleword, which is compared with the top of the stack.
 Original instructions set flags C0, C2 and C3 in the FPU status word register. After implementing FPU as the integral unit of the processor, a new set of instructions appeared that set flags in the FLAGS register directly. There are **fcomi**, **fcomip**, **fucomi** and **fucomip**. Their first argument is always ST(0), the second is another FPU register. Original instructions set flags C0, C2 and C3 in the FPU status word register. After implementing FPU as the integral unit of the processor, a new set of instructions appeared that set flags in the FLAGS register directly. There are **fcomi**, **fcomip**, **fucomi** and **fucomip**. Their first argument is always ST(0), the second is another FPU register.
 +To the group of the comparison instructions also belong **fxam** and **ftst** instructions. The **fxam** instruction classifies the value of ST(0), while the **ftst** instruction compares ST(0) with the value of 0.0. They return the information in C0, C2 and C3 flags.
  
 ===== Transcendental instructions ===== ===== Transcendental instructions =====
 +The transcendental instructions perform calculations of advanced mathematical functions.
 +The **fsin** instruction calculates the sine, while the **fcos** calculates the cosine of the argument stored in ST(0). The **fsincos** calculates both sine and cosine with the same instruction. The sine is returned in ST(1), the cosine in ST(0). The **fptan** instruction calculates the partial tangent and **fpatan** the partial arctangent. After calculating the tangent, the value of 1.0 is pushed onto the stack to make it easier to calculate cotangent afterwards by execution **fdivr** instruction. The partial means that this instruction handles only a limited range of input arguments.
 +The instructions for exponential and logarithmic functions are summarised in table {{ref>ftrans}}.
 +<table ftrans>
 +<caption>Transcendental arithmetic instructions</caption>
 +^ Mnemonic     ^ operation                              ^ note on operands        ^
 +| **f2xm1**    | {{ :en:multiasm:cs:f2xm1.png?105 }}    |                         |
 +| **fyl2x**    | {{ :en:multiasm:cs:fyl2x.png?105 }}    | y is ST(1); x is ST(0)  |
 +| **fyl2xp1**  | {{ :en:multiasm:cs:fyl2xp1.png?105 }}  | y is ST(1); x is ST(0)  |
 +</table>
 +
 +===== FPU control instructions =====
 +The FPU control instructions help the programmer to save and restore the contents of chosen registers if there is a need to use them in an interrupt handler or inside a function. It is also possible to initialise the state of the FPU unit or clear errors.
 +The **fincstp** increments and **fdecstp** decrements the FPU register stack pointer.
 +The following set of instructions can perform error checking while execution (instructions without "N") or perform the operation without checking for error conditions (instructions without "N").
 +The **finit** and **fninit** initialise the FPU (after checking error conditions or without checking error conditions).
 +The **fclex** and **fnclex** clear floating-point exception flags.
 +The **fstcw** and **fnstcw** store the FPU control word.
 +The **fldcw** loads the FPU control word.
 +The **fstenv** and **fnstenr** store the FPU environment. The environment consists of the FPU control word, status
 +word, tag word, instruction pointer, data pointer, and last opcode register.
 +The **fldenv** loads the FPU environment.
 +The **fsave** and **fnsave** save the FPU state. The state is the operating environment and full register stack.
 +The **frstor** restores the FPU state.
 +The **fstsw** and **fnstsw** store the FPU status word. There is no instruction for restoring the status word.
 +The **wait** or **fwait** waits for the FPU to finish the operation.
 +The **fnop** instruction is the no operation instruction for the FPU.
en/multiasm/papc/chapter_6_10.1761905172.txt.gz · Last modified: 2025/10/31 10:06 by ktokarz
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