Data Types and Encoding

Higher-level programming languages define several data types; some languages don’t need to determine the data type because during program compilation (or interpretation), the value type is automatically assigned to them. The first type of division can be made between real and integer numbers. Then the integers can also be divided into only positive values and the values that can be positive or negative. The remaining division can be performed by determining how many bytes are needed to store the largest required value.

Many instructions include additional suffixes to indicate the length of the data used. As an example of multiple data lengths, load/store instructions will be used. Loading floating-point (real numbers) values is described in the next chapter. All the following examples use integers. One 64-bit register can be split into eight 8-bit values, four 16-bit values, or two 32-bit values. It is important to remember that the entire 64-bit register will be used whether storing an 8-bit or a 16-bit value. The remaining bytes in the register depend on the instruction used.

LDR X0, [X1] @ fill the register X0 with the data located at address stored in X1 register

STR X1, [X2] @ store the content from register X1 into the memory at memory address given in the X2 register

The LDR and STR instructions are basic instructions that load or store the entire register from or to memory. It means that 8 bytes or 4 bytes are loaded into the register. Remember that register size depends on the notation used: Xn or Wn. To load a single byte, use the LDRB and LDRSBinstructions. For these instructions, the destination register can be addressed only as a 32-bit register.

LDRB W0, [X1]

LDRSB W0, [X1]

Similar destination register restrictions apply to 16-bit, LDRH, and LDRSH instructions. These restrictions stem from the fact that there is no sign extension for 64-bit registers, only for 32-bit registers. Any write to a 32-bit register automatically clears the upper bits in the whole 64-bit register. To store a byte or half-word in memory, the data must be held in the 32-bit register before it is written. And only the least significant bytes are stored by use of the STRB or STRH instruction.

Overall, by the ARMv8.0, a new feature to the processor is added. In this section, the main focus is on endianness, and the feature named “FEAT_MixedEnd” from ARMv8 processors allows programmers to control the endianness of the memory. This means that the ARMv8 have implemented both little-endian and big-endian. For the Raspberry PI v5 running in AArch64, the higher exception layers control the endianness for the lower exception layer. For example, the code running in the Exception Level EL1 layer can control the endianness of the EL0 Exception Level. Note that if the Linux OS is already running on the Raspberry PI, then the kernel EL1 endianness should not be changed, because the OS is running on the EL1 layer, and now no OS can switch endianness at runtime. As both modes are supported in the ARMv8, there might be a need to figure out what settings are set for EL0 concerning endianness. The ID_AA64MMFR0_EL1 is an AArch64 Memory Model Feature register that holds information about endianness. For the program code in the register ID_AA64MMFR0_EL1 bits [11:8] indicate the endianness features for the whole CPU.

For example, in the register ID_AA64MMFR0_EL1, the BigEndEL0 bits indicate the support for mixed-endian at Exception Level EL0. If the value is nonzero, then The SCTLR_EL1.E0E register bit field is controlled through higher Exception Levels. Assuming that our designed code will be executed in Exception Level EL0, then … ←- {not finished}