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--- en:multiasm:cs:chapter_3_9 [2025/01/07 12:12] – [Superscalar] ktokarz
+++ en:multiasm:cs:chapter_3_9 [2025/12/12 08:28] (current) – [Modern Processors: Pipeline, Superscalar, Branch Prediction, Hyperthreading] ktokarz
@@ Line 1: / Line 1: @@
-====== Modern Processors: Pipeline, Superscalar, Branch Prediction, Hyperthreading ======
+====== Modern Processors: Cache, Pipeline, Superscalar, Branch Prediction, Hyperthreading ======
 Modern processors have a very complex design and include many units responsible mainly for shortening the execution time of the software.
+===== Cache =====
+Cache memory forms a layer in the memory hierarchy that intermediates between the main memory and the processor registers. The main reason for the introduction of cache memory is that main memory based on DRAM technology is much slower than the processor, which is based on static technology. The cache exploits two software features: spatial locality and temporal locality. Spatial locality results from the fact that the processor executes code, which in most cases is a sequence of instructions arranged directly behind each other. Temporal locality arises because programs often run in loops, repeatedly working on a single set of data over short intervals. In both cases, a larger fragment of a program or data can be loaded into the cache and operated on without having to access the main memory each time. Main memory is designed to significantly speed up reading and writing data in blocks compared to accessing random addresses. These properties allow a code fragment to be read in its entirety from main memory into the cache and executed without the need to access RAM for each instruction separately. In the case of data, the processor performs calculations after reading a block into the cache and then stores the results in a single write sequence.
+In modern processors, the cache is divided into several levels, usually three. The first-level cache (L1) is the closest to the processor, the fastest, and is usually divided into separate instruction and data caches. The second-level cache (L2) is shared, slower and usually larger than the L1 cache. The largest and the slowest is the third-level cache (L3). It is closest to the computer's main memory. An average latency of L1 cache is 1-2 ns, L2 has a latency of 3-5 ns, and L3 about 10-20 ns. An example i7 processor, for each core, has 32 KB of L1 code cache, 32 KB of L1 data cache, and 256 KB of L2 cache for both code and data. The third-level cache (L3) is 8 MB and is shared by all cores.
+Besides the size, important parameters of cache are the line length and associativity.
+Length of the line is usually expressed in bytes. It tells how many bytes are stored in a single, smallest possible data fragment. It also determines at what addresses such a data fragment starts in main memory. For example, if the cache line length is 64 bytes and memory is byte-organised, the block of memory copied to cache always starts at an address evenly divisible by 64.
+Associativity tells how many cache lines can be used to store the block from a specific address. If the block can go to any cache line, the cache is fully associative. If there is only one possible location, the cache is named direct-mapped. A fully associative cache is more flexible, but complex and expensive. Direct-mapped cache is simple, but it can cause data conflicts if two blocks of memory which should go to the same cache line need to be loaded. In real processors, the compromise solution is often implemented, which enables storing each block in 2, 4 or 8 different cache lines. It is named 2-, 4- or 8-way associative cache. This solution significantly reduces conflicts and ensures good performance at a reasonable cost.
 ===== Pipeline =====
-As was described in the previous chapter, executing a single instruction requires many actions which must be performed by the processor. We could see that each step, or even substep, can be performed by a separate logical unit. This feature has been used by designers of modern processors to create a processor in which instructions are executed in a pipeline. A pipeline is a collection of logical units that execute many instructions at the same time - each of them at a different stage of execution. If the instructions arrive in a continuous stream, the pipeline allows the program to execute faster than a processor that does not support the pipeline. Note that the pipeline does not reduce the time of execution of a single instruction, it increases the throughput of the instruction stream.
+As was described in the previous chapter, executing a single instruction requires many actions which must be performed by the processor. We could see that each step, or even substep, can be performed by a separate logical unit. This feature has been used by designers of modern processors to create a processor in which instructions are executed in a pipeline. A pipeline is a collection of logical units that execute many instructions at the same time - each of them at a different stage of execution. If the instructions arrive in a continuous stream, the pipeline allows the program to execute faster than a processor that does not support the pipeline. Note that the pipeline does not reduce the time of execution of a single instruction. It increases the throughput of the instruction stream.
-A simple pipeline is implemented in AVR microcontrollers. It has two stages, which means that while one instruction is executed another one is fetched as shown in Fig {{ref>pipelineavr}}.
+A simple pipeline is implemented in AVR microcontrollers. It has two stages, which means that while one instruction is executed, another one is fetched as shown in Fig {{ref>pipelineavr}}.
 <figure pipelineavr>
-{{ :en:multiasm:cs:pipeline_AVR.png?600 |Simple 2-stage pipeline in AVR microcontroller}}
+{{ :en:multiasm:cs:pipeline_AVR.png?600 |Simple 2-stage pipeline in an AVR microcontroller}}
 <caption>Simple 2-stage pipeline in AVR microcontroller</caption>
 </figure>
@@ Line 17: / Line 27: @@
 </figure>
-Modern processors implement longer pipelines. For example, Pentium III used the 10-stage pipeline, Pentium 4 20-stage, and Pentium 4 Prescott even a 31-stage pipeline. Does the longer pipeline mean faster program execution? Everything has benefits and drawbacks. The undoubted benefit of a longer pipeline is more instructions executed at the same time which gives the higher instruction throughput. But the problem appears when branch instructions come. While in the instruction stream a conditional jump appears the processor must choose what way the instruction stream should go. Should the jump be taken or not? The answer usually is based on the result of the preceding instruction and is known when the branch instruction is close to the end of the pipeline. In such a situation in modern processors, the branch prediction unit guesses what to do with the branch. If it misses, the pipeline content is invalidated and the pipeline starts operation from the beginning. This causes stalls in the program execution. If the pipeline is longer - the number of instructions to invalidate is bigger. That's why Intel decided to return to shorter pipelines. In modern microarchitectures, the length of the pipeline varies between 12 and 20.
+Modern processors implement longer pipelines. For example, Pentium III used the 10-stage pipeline, Pentium 4 20-stage pipeline, and Pentium 4 Prescott even used a 31-stage pipeline. Does the longer pipeline mean faster program execution? Everything has benefits and drawbacks. The undoubted benefit of a longer pipeline is more instructions executed at the same time, which gives a higher instruction throughput. But the problem appears when branch instructions come. While a conditional jump appears in the instruction stream, the processor must choose which way the stream should follow. Should the jump be taken or not? The answer is usually based on the result of the preceding instruction and is known when the branch instruction is close to the end of the pipeline. In such a situation, in modern processors, the branch prediction unit guesses what to do with the branch. If it misses, the pipeline content is invalidated, and the pipeline starts operation from the beginning. This causes stalls in the program execution. If the pipeline is longer, the number of instructions to invalidate is bigger. In modern microarchitectures, the length of the pipeline varies between 12 and 20.
 ===== Superscalar =====
-The superscalar processor increases the speed of program execution because it can execute more than one instruction during a clock cycle. It is realised by simultaneously dispatching instructions to different execution units on the processor. The superscalar processor doesn't implement two or more independent pipelines, rather decoded instructions are sent for further processing to the chosen execution unit as shown in Fig. {{ref>superscalar}}.
+The superscalar processor increases the speed of program execution because it can execute more than a single instruction during a clock cycle. It is realised by simultaneously dispatching instructions to different execution units on the processor. The superscalar processor can, but doesn't have to, implement two or more independent pipelines. Rather, decoded instructions are sent for further processing to the chosen execution unit as shown in Fig. {{ref>superscalar}}.
 <figure superscalar>
@@ Line 28: / Line 38: @@
 </figure>
-In the x86 family first processor with two paths of execution was Pentium with U and V pipelines. Modern x64 processors like i7 implement six execution units. Not all execution units have the same functionality, for example, In the i7 processor, every execution unit has different possibilities, as presented in table {{ref>executionunits}}.
+In the x86 family first processor with two paths of execution was the Pentium with two execution units called U and V. Modern x64 processors like i7 implement six execution units. Not all execution units have the same functionality. For example, in the i7 processor, every execution unit has different possibilities, as presented in table {{ref>executionunits}}.
 <table executionunits>
@@ Line 41: / Line 51: @@
 </table>
-<note info>
-The real path of instruction processing is much more complex. Additional techniques are implemented to achieve better performance e.g. out-of-order execution, and register renaming. They are performed automatically by the processor and the assembler programmer does not influence their behaviour.
-</note>
 ===== Branch prediction =====
-Branch Prediction is a technique used in computer hardware to guess the outcome of conditional branch instructions, helping to reduce delays in program execution by predicting which path the program will take based on historical data and patterns.
+As it was mentioned, the pipeline can suffer invalidation if the conditional branch is not properly predicted. The branch prediction unit is used to guess the outcome of conditional branch instructions. It helps to reduce delays in program execution by predicting the path the program will take. Prediction is based on historical data and program execution patterns.
+There are many methods of predicting the branches. In general, the processor implements the buffer with the addresses of the last few branch instructions with a history register for every branch. Based on history, the branch prediction unit can guess if the branch should be taken.
+===== Hyperthreading =====
+Hyper-Threading Technology is an Intel approach to simultaneous multithreading technology, which allows the operating system to execute more than one thread on a single physical core.
+For each physical core, the operating system defines two logical processor cores and shares the load between them when possible. The hyperthreading technology uses a superscalar architecture to increase the number of instructions that operate in parallel in the pipeline on separate data. With Hyper-Threading, one physical core appears to the operating system as two separate processors. The logical processors share the execution resources, including the execution engine, caches, and system bus interface. Only the elements that store the architectural state of the processor are duplicated, including essential registers for code execution.
+<note info>
+The real path of instruction processing is much more complex. Additional techniques are implemented to achieve better performance, e.g. out-of-order execution and register renaming. They are performed automatically by the processor, and the assembler programmer does not influence their behaviour.
+</note>

en/multiasm/cs/chapter_3_9.1736251922.txt.gz · Last modified: 2025/01/07 12:12 by ktokarz