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--- en:multiasm:cs:chapter_3_13 [2025/01/08 20:46] – ktokarz
+++ en:multiasm:cs:chapter_3_13 [2025/12/12 09:47] (current) – ktokarz
@@ Line 1: / Line 1: @@
 ====== DMA ======
-Direct memory access.
+Direct memory access (DMA) is the mechanism for fast data transfer between peripherals and memory. In some implementations, it is also possible to transfer data between two peripherals or from memory to memory. DMA operates without the activity of the processor. No software is executed during the DMA transfer. It must be supported by a processor and peripheral hardware, and there must be a DMA controller present in the system. The controller plays the main role in transferring the data.
-Peripheral device reads/writes directly from/to memory.
-No program execution is needed to transfer data.
+The DMA controller is a specialised unit which can control the data transfer process. It implements several channels, each containing the address register, which is used to address the memory location and a counter to specify how many cycles should be performed. The address and counter registers have corresponding temporal address and counter registers updated after every single transfer. The address register and counter must be programmed by the processor. It is usually done in the system startup procedure. The system with an inactive DMA controller is presented in Fig.{{ref>DMAinactive}}.
-Faster data transfer.
-Buses are controlled with DMA controller.
+<figure DMAinactive>
-No processor RD or WR cycles.
+{{ :en:multiasm:cs:DMA_inactive.png?600 |System with inactive DMA controller}}
+<caption>System with inactive DMA controller</caption>
+</figure>
+The process of data transfer is done in some steps. Let us consider the situation when a peripheral has some data to be transferred.
+  * peripheral signals the request to transfer data (DREQ).
+  * DMA controller forwards the request to the processor (HOLD).
+  * The processor accepts the DMA cycle (HLDA) and switches off from the buses.
+  * DMA controller generates the address on the address bus and sends the acknowledge signal to the peripheral (DACK).
+  * Peripheral sends the data on the data bus.
+  * DMA generates a write signal to store data in the memory.
+  * DMA controller updates the address register and the counter.
+  * If the counter reaches zero, data transfer stops.
+Everything is done without any action of the processor. No program is fetched and executed. Because everything is done by hardware, the transfer can be done in one memory access cycle, so much faster than by the processor. Data transfer by the processor is significantly slower because it requires at least four instructions of program execution and two data transfers: one from the peripheral and another to the memory for one cycle. The system with an active DMA controller is presented in Fig.{{ref>DMAactive}}.
+<figure DMAactive>
+{{ :en:multiasm:cs:DMA_active.png?600 |System performing DMA transfer}}
+<caption>System performing DMA transfer</caption>
+</figure>
+DMA transfer can be done in some modes:
+  * Single - one transfer at a time
+  * Block (burst) - block of data at a time
+  * On-demand - as long as the I/O device accepts transfer
+  * Cycle stealing - one cycle DMA, one CPU
+  * Transparent - DMA works when the CPU is executing instructions
+DMA controllers are implemented in personal computers, but also in advanced microcontrollers and systems on a chip, to support data transfers between internal memory and internal peripherals.

en/multiasm/cs/chapter_3_13.1736369209.txt.gz · Last modified: 2025/01/08 20:46 by ktokarz