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-====== Optimisation (DRAFT) ======
-Optimisation strongly depends on the microarchitecture of the processor. Some optimisation recommendations change together with new versions of processors. Producers usually publish the most up-to-date recommendations. The last release of the Intel documentation is "Intel® 64 and IA-32 Architectures Optimization" ((https://www.intel.com/content/www/us/en/developer/articles/technical/intel64-and-ia32-architectures-optimization.html)). AMD published the document "Software Optimization Guide for the AMD Zen5 Microarchitecture" ((https://docs.amd.com/v/u/en-US/58455_1.00)).
-A selection of specific optimisation recommendations is described in this section.
-===== The use of inc and dec instructions =====
-It is natural for programmers to use **inc** or **dec** instructions to increment or decrement the variable. They are simple and appear to be executed faster than addition and subtraction with a constant "1". The **inc** and **dec** are single-byte instructions, while **add** and **sub** with the argument as a constant consume at least one byte more. The problem with **inc** and **dec** instructions stems from the fact that they do not modify all flags, whereas **add** and **sub** modify all. Modifying all flags frees the processor from the need to wait for previously executed instructions to finish their operation in terms of flag modification. Intel recommends replacing **inc** and **dec** with **add** and **sub** instructions, but compilers do not always consider this recommendation.
-===== Versions of logic instructions =====
-While new extensions are introduced, several new instructions appear. In addition to advanced data processing instructions, simple logic instructions are also implemented. Previous versions of instructions are extended to operate with the latest, bigger registers. This may lead to confusion about which instruction to use, especially when they perform the same operation and give the same result. Let's consider three logic XOR instructions **pxor**, **xorps** and **xorpd**. All of them can operate on 128-bit XMM registers performing the bit-wise logic XOR function. At first sight, the instruction choice is meaningless - the result will be the same. In reality, the selection of the instruction matters. The performance analysis yields a result that, in different situations, the execution time can be longer or shorter. A deeper analysis reveals that when previous calculations are performed with integers, it is better to use integer operation **pxor**; if the data is floating-point, it is better to use the floating-point version **xorps** or **xorpd**. There is a section in the Intel optimisation manual about mixing SIMD data types. It is recommended to use packed-single instead of packed-double when possible.
-===== Data placement =====
-It is recommended to place variables in the memory at their natural boundaries. It means that if the data is 16 bytes, the address should be evenly divisible by 16. For 8-byte data, the address should be divisible by 8.
-===== Registers use =====
-It is recommended to use registers instead of memory for scalar data if possible. Keeping data in registers eliminates the need to load and store it in memory.
-===== Pause instruction =====
-It is a common method to pause the program execution and wait for an event for a short period in a spin loop. In case of a brief waiting period, this method is more efficient than calling an operating system function, which waits for an event. In modern processors, the **pause** instruction should be used inside such a loop. It helps the internal mechanisms of the processor by allocating hardware resources for a while to another logical processor.
-===== Cache temporal locality =====
-The term temporal locality refers to the fact that if data is used, it remains in a cache for a certain amount of time until other data is loaded into the cache. It is efficient to keep data in a cache instead of reloading it. This feature helps improve performance in situations where the program uses the same variables repeatedly, e.g. in a loop.
-In a situation where the data processed exceeds half the size of a level 1 cache, it is recommended to use the non-temporal data move instructions **movntq** and **movntdq** to store data from registers to memory. These instructions are hints to the processor to omit the cache if possible. It doesn't mean that the data is immediately stored directly in memory. It can remain in the internal processor's buffers, and it is likely that the last version is not visible to other units of the computer. It is the programmer's responsibility to synchronise the data using the **sfence** (Store Fence) instruction.
-===== Cache support instructions =====
-In modern microarchitectures, the cache memory is essential for improving performance. In general, the processor handles cache memory in the most efficient way possible; however, it is easy to write a program that prevents the processor from utilising this mechanism effectively. The rules for helping processors to use cache to achieve the best performance are:
-There are also instructions which allow the programmer to support the processor with cache utilisation.
-  * **movntq** saving the contents of the MMX register, bypassing cache
-  * **movntps** write the contents of the SSE register, bypassing cache
-  * **maskmovq** write selected bytes from the MMX register, bypassing cache
-  * **movntdqa** non-temporal aligned move
-Fence instructions guarantee that the load and/or store instructions before the fence are completed before the corresponding instruction after the fence.
-  * **spence** force the memory–cache synchronisation after store instructions
-  * **lfence** force the memory–cache synchronisation after load instructions
-  * **mfence** force the memory–cache synchronisation after load and store instructions
-  * **prefetch** a hint to the processor, which indicates that the memory area should be considered higher in the hierarchy cache
-  * **clflush** flushes a Cache Line from all levels of cache.
-===== Cache temporal locality =====
-The term temporal locality refers to the fact that if data is used, it remains in a cache for a certain amount of time until other data is loaded into the cache. It is efficient to keep data in a cache instead of reloading it. This feature helps improve performance in situations where the program uses the same variables repeatedly, e.g. in a loop.
-In a situation where the data processed exceeds half the size of a level 1 cache, it is recommended to use the non-temporal data move instructions **movntq** and **movntdq** to store data from registers to memory. These instructions are hints to the processor to omit the cache if possible. It doesn't mean that the data is immediately stored directly in memory. It can remain in the internal processor's buffers, and it is likely that the last version is not visible to other units of the computer. It is the programmer's responsibility to synchronise the data using the **sfence** (Store Fence) instruction.
-===== Further reading =====
-The essential readings in an optimisation topic are the vendors' optimisation guides mentioned at the beginning of this section.
-An exceptional position about optimisation in x64 processors is by Agner Fog((https://agner.org/optimize/optimizing_assembly.pdf)). This is a must-read for programmers who want to optimise their programs. Thanks to the author's extensive knowledge and hard work, this guide documents various tricks, as well as the execution times of individual processor instructions. It is mentioned in almost all internet articles and blogs about optimisation.
-Interesting Understanding Windows x64 Assembly tutorial ((https://sonictk.github.io/asm_tutorial/#debuggingassembly/thetools/radare2/cutterandida)) not only about optimisation but also about using low-level programming in Windows.

en/multiasm/papc/chapter_6_16.1763811772.txt.gz · Last modified: 2025/11/22 11:42 by ktokarz