======ESP32-Hx Family======
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=====ESP32-H2=====
==ESP32-H2 General Information==
ESP32-H2 is a family of microcontrollers (SoC) that combines IEEE 802.15.4 connectivity with Bluetooth 5 (LE). The system does not have a Wi-Fi protocol, but Thread and Zigbee protocols are available. ESP32-H2 has been certified as a “Zigbee-Compliant Platform” and has officially become a “Thread-Certified 1.3.0 Component”. The SoC is powered by a single-core, 32-bit RISC-V microcontroller that can be clocked up to 96 MHz. The ESP32-H2 has been designed especially for connected devices with low power consumption and security in mind. ESP32-H2 has 320 KB of SRAM with 16 KB of Cache, 128 KB of ROM, 4 KB LP of memory, and a built-in 2 MB or 4 MB SiP flash. It has 19 programmable GPIOs supporting ADC, SPI, UART, I2C, I2S, RMT, GDMA and LED PWM.
For now, the ESP32-H2 family documentation is available as preliminary information only.
== ESP32-H2 Architecture Overview ==
Figure {{ref>esp32h2_functions}} shows a functional block diagram of the ESP32-H2 chip. Main common features of the ESP32-H2 are ((https://www.espressif.com/sites/default/files/documentation/esp32-h2_datasheet_en.pdf)):
**Processors**
* **Main processor:** 32-bit RISC-V single-core CPU up to 96MHz,
* **Cores**: 1
**Wireless connectivity**
* **Bluetooth:** v5.0 Bluetooth Low Energy (BLE) ( speed: 125 Kbps - 2 Mbps),
* ** 802.15.4-2015: ** up to 250 kbps; stacks include Thread 1.3, Zigbee 3.0, Matter, HomeKit, MQTT.
**Memory: Internal memory**
* **Embedded flash** 2 or 4 MB,
* **ROM:** 128 kB (for booting and core functions),
* **SRAM:** 320 kB (for data and instructions),
* **LP memory:** 4 KB of SRAM that can be accessed by the CPU. It can retain data in deep sleep mode,
* ** eFuse ** - 4 Kbit: 1792 bits are reserved for user data, such as encryption key and device ID.
**Peripheral Input/Output**
* 19 x GPIO,
* 2 x 12-bit ADCs (analog-to-digital converter) up to 5 channels,
* Internal temperature sensor,
* 3 × SPI (Serial Peripheral Interface),
* 2 x UART (universal asynchronous receiver/transmitter),
* 2 × I²C (Inter-Integrated Circuit),
* 1 × I²S (Integrated Inter-IC Sound),
* LED PWM up to 6 channels,
* General DMA with - 3 x Tx + 3 x Rx,
* PWM for Motor control,
* 1 × TWAI® controller compatible with ISO 11898-1 (CAN Specification 2.0),
* 1 x Parallel IO controller (PARLIO),
* USB Serial/JTAG controller.
**Security**
* Secure boot,
* Flash encryption,
* 4096-bit OTP, up to 1792-bit for customers,
* Cryptographic hardware acceleration:
* AES-128/256,
* SHA accelerator,
* RSA accelerator 3072 bit,
* random number generator (RNG),
* digital signature.
Since the processor documentation is only available for the pre-production version, it may change in the final version
==ESP32-H2 Development Boards==
There are not many prototype kits with ESP32-H2 SOCs on the market yet. One of them is produced by the Espressif company itself:
* Espressif - ESP32-H2-DevkitM-1((https://docs.espressif.com/projects/espressif-esp-dev-kits/en/latest/esp32h2/esp32-h2-devkitm-1/user_guide.html))