======ESP32-Cx Family======
{{:en:iot-open:czapka_b.png?50| General audience classification icon }}{{:en:iot-open:czapka_e.png?50| General audience classification icon }}\\
==ESP32-C2 General Information==
The ESP32-C2 (ESP8684) ((https://www.espressif.com/sites/default/files/documentation/esp8684_datasheet_en.pdf)) family is a series of microcontrollers developed by Espressif Systems. It's based on the RISC-V architecture and is designed to offer ultra-low power and small size for various IoT (Internet of Things) applications. This family of microcontrollers has been designed to target simple, high-volume, and low-data-rate IoT applications, such as smart plugs and smart light bulbs. ESP32-C2 is also supported by Espressif's AIoT Private Cloud platform, ESP RainMaker® and supports Matter, a smart-home connectivity protocol that runs on any IP-supporting network stack.
The ESP32-C2 microcontrollers come with several distinctive features:
* RISC-V Core: The ESP32-C2 is based on the RISC-V architecture, an open-source instruction set architecture (ISA). This differs from the ESP32 series' usual Tensilica Xtensa LX6 architecture.
* Connectivity: Like other ESP32 modules, the ESP32-C2 features built-in Wi-Fi and Bluetooth 5 LE connectivity. This allows it to connect to the internet and communicate with other devices over short distances.
* Low Power Consumption: ESP32-C2, like other ESP32 variants, supports low-power modes, which is crucial for battery-powered and energy-efficient IoT applications.
* Rich Peripheral Interface Support: It includes a variety of peripherals such as UART, I2C, SPI, ADC, and more, making it versatile for different applications.
* Security Features: The ESP32-C2 family includes various security features, such as secure boot, flash encryption, secure storage, and cryptographic accelerators.
* Compact Form Factor: The ESP32-C2 family is designed in a very compact form factor (4mm x 4mm), which is crucial for applications with limited space or miniaturization.
* Cost-Effective Solution: These microcontrollers offer a cost-effective solution for IoT applications without compromising essential features and performance.
For now the ESP32-C2 family includes the following chips in mass production (figure {{ref>esp32_c2}}):
* ESP8684.
{{ :en:iot-open:hardware2:esp8684.jpg?200 | ESP32-C2}}
ESP32-C2
===== ESP32-C2 =====
== ESP32-C2 Architecture Overview ==
Figure {{ref>esp32c2_functions}}((https://www.espressif.com/sites/default/files/documentation/esp8684_datasheet_en.pdf)) shows functional block diagram of ESP32-C2 chip. The main common features of the ESP32-C2 are:
**Processors**
* **Main processor:** 32-bit RISC-V single-core CPU,
* **Cores**: 1 up to 120 MHz,
* External main crystal clock,
* External 32 kHz crystal oscillator for RTC or internal RC.
**Wireless connectivity**
* **WiFi:** 802.11 b/g/n (802.11n @ 2.4 GHz up to 72.2 Mbit/s) with simultaneous Infrastructure BSS Station mode/SoftApp mode/Promiscuous mode,
* **Bluetooth:** v5.0 Bluetooth Low Energy (BLE) ( speed: 125 Kbps - 2 Mbps) with multiple advertisement sets
**Memory: Internal memory**
* **Embedded flash** 1, 2, 4 MB,
* **ROM:** 576 kB (for booting and core functions),
* **SRAM:** 272 kB (16kB for cache),
* ** eFuse ** - 1 Kbit -256 bits reserved for encryption key and device ID.
**Peripheral Input/Output**
* 14 x GPIO,
* 3 × SPI (Serial Peripheral Interface),
* 2 x UART (universal asynchronous receiver/transmitter),
* 1 × I²C Master (Inter-Integrated Circuit),
* LED PWM up to 6 channels,
* 1 x 12-bit ADCs (analogue-to-digital converter) up to 5 channels,
* General DMA controller (GDMA), with 1 transmit channel and 1 receive channel.
** Power Modes **
* Active Mode,
* Modem-sleep mode,
* Light-sleep mode,
* Deep-sleep mode.
**Security**
* Secure boot,
* Flash encryption,
* 1024-bit OTP, up to 256-bit for customers,
* Cryptographic hardware acceleration:
* SHA1/SHA224/SHA256 (FIPS PUB 180-4),
* ECC,
* random number generator (RNG),
* clock glitch filter.
{{ :en:iot-open:hardware2:esp32c2block.jpg?400 | ESP32-C2 functional block diagram}}
ESP32-C2 functional block diagram
For now the ESP32-C2 family includes the following chips in mass production (table {{ref>esp32c2_chips}}):
===== ESP32-C3 =====
==ESP32-C3 General Information==
The ESP32-C3 family is a series of microcontrollers developed by Espressif Systems. It's based on the RISC-V architecture and is designed to offer low-power and cost-effective solutions for various IoT (Internet of Things) applications. These chips integrate WiFi connectivity, have low power consumption, and offer different peripheral interfaces. They suit diverse IoT projects, enabling developers to create connected devices efficiently. The new ESP32-C3 family is known for its compact size, low power consumption, and integration of WiFi capabilities. These microcontrollers balance performance and power efficiency, making them suitable for battery-powered IoT devices. They support a variety of interfaces like SPI, I2C, UART, and ADC, enabling connectivity and interactions with various sensors and devices. This family of microcontrollers is viral in smart home devices, wearables, and other IoT applications that require wireless connectivity.
The ESP32-C3 microcontrollers come with several distinctive features:
* RISC-V Core: One of the notable aspects of the ESP32-C3 family is the use of the RISC-V instruction set architecture, which provides efficiency and flexibility. This architecture allows for customization and optimization, balancing performance and power consumption.
* WiFi Connectivity: These chips integrate WiFi connectivity, enabling devices to connect to wireless networks, making them ideal for IoT applications that require internet connectivity.
* Low Power Consumption: The ESP32-C3 family is designed to focus on low power consumption, which is essential for battery-powered or energy-efficient IoT devices. This makes them suitable for applications where power efficiency is a priority.
* Rich Peripheral Interface Support: The microcontrollers have various peripheral interfaces, such as SPI, I2C, UART, PWM, and ADC. These interfaces allow easy integration with multiple sensors, displays, and other devices, enhancing the versatility of applications that can be developed.
* Security Features: The ESP32-C3 family includes various security features like secure boot, flash encryption, secure storage, and cryptographic accelerators. These elements contribute to the overall security of the devices developed using these microcontrollers.
* Compact Form Factor: The ESP32-C3 family is designed in a compact form factor, which is advantageous for applications where limited space or miniaturization is a concern.
* Cost-Effective Solution: These microcontrollers offer a cost-effective solution for IoT applications without compromising essential features and performance.
For now the ESP32-C3 family includes the following chips in mass production (table {{ref>esp32c3_chips}}):
== ESP32-C3 Architecture Overview ==
Figure {{ref>esp32c3_functions}} shows a functional block diagram of the ESP32-C3 chip. Main common features of the ESP32-C3 are: ((https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf))
**Processors**
* **Main processor:** 32-bit RISC-V single-core CPU,
* **Cores**: 1 up to 160 MHz,
* External main crystal clock,
* External 32 kHz crystal oscillator for RTC or internal RC.
**Wireless connectivity**
* **WiFi:** 802.11 b/g/n (802.11n @ 2.4 GHz up to 150 Mbit/s) with simultaneous Infrastructure BSS Station mode/SoftApp mode/Promiscuous mode.
* **Bluetooth:** v5.0 Bluetooth Low Energy (BLE) ( speed: 125 Kbps - 2 Mbps) with multiple advertisement sets
**Memory: Internal memory**
* **Embedded flash** 4 MB
* **ROM:** 384 kB (for booting and core functions).
* **SRAM:** 400 kB (16kB for cache).
* **RTC fast SRAM:** 8 kB
* ** eFuse ** - 4 Kbit - 1792 bits reserved for encryption key and device ID
**Peripheral Input/Output**
* 22 or 16 GPIO
* 2 x 12-bit ADCs (analog-to-digital converter) up to 6 channels,
* General DMA controller (GDMA), with 3 transmit channels and 3 receive channels,
* 1 × I²C (Inter-Integrated Circuit),
* 2 x UART (universal asynchronous receiver/transmitter),
* 1 × TWAI® controller compatible with ISO 11898-1 (CAN Specification 2.0),
* 3 × SPI (Serial Peripheral Interface),
* 1 × I²S (Integrated Inter-IC Sound),
* LED PWM up to 6 channels,
* Internal temperature sensor,
* USB Serial/JTAG controller.
**Security**
* Secure boot,
* Flash encryption,
* 4096-bit OTP, up to 1792-bit for customers,
* Cryptographic hardware acceleration:
* AES-128/256,
* SHA accelerator,
* RSA accelerator,
* random number generator (RNG),
* digital signature.
{{ :en:iot-open:hardware2:esp32c3block.jpg?400 | ESP32-C3 functional block diagram}}
ESP32-C3 functional block diagram
==ESP32-C3 Modules==
Espressif also produces modules that are more integrative and more convenient for amateurs and developers to use. The following modules are currently available:
* ESP32-C3-Mini-1/1U((https://www.espressif.com/sites/default/files/documentation/esp32-c3-mini-1_datasheet_en.pdf))(figure {{ref>esp32_c3_mini1}}) ,
* ESP32-C3-WROOM-02/02U((https://www.espressif.com/sites/default/files/documentation/esp32-c3-wroom-02_datasheet_en.pdf))(figure {{ref>esp32_c3_wroom}}).
{{ :en:iot-open:hardware2:esp32c3mini1.jpg?200 | ESP32-C3-Mini-1/1U}}
==ESP32-C3 Development Kits==
Development kits are the most convenient for quick application or to check the capabilities of processors. Espressif manufactures them and many companies specialising in producing prototype circuits. The following are some of the most versatile modules
* Espressif - ESP32-C3-DevkitM-1((https://docs.espressif.com/projects/esp-idf/en/latest/esp32c3/hw-reference/esp32c3/user-guide-devkitm-1.html))(figure {{ref>esp32_c3_devkitm}}), \\
* Espressif - ESP32-C3-DevkitC-02((https://docs.espressif.com/projects/esp-idf/en/latest/esp32c3/hw-reference/esp32c3/user-guide-devkitc-02.html))(figure {{ref>esp32_c3_devkitc}}), \\
* Espressif - ESP32-C3-LCDKit ((https://docs.espressif.com/projects/espressif-esp-dev-kits/en/latest/esp32c3/esp32-c3-lcdkit/user_guide.html))(figure {{ref>esp32_c3_devkitlcd}})
* Adafruit - QT Py ESP32-C3 WiFi Dev Board with STEMMA QT((https://www.adafruit.com/product/5405)) (figure {{ref>esp32_c3_adafruit}}), \\
* Seeed Studio - XIAO ESP32C3 ((https://wiki.seeedstudio.com/XIAO_ESP32C3_Getting_Started/)) (figure {{ref>esp32_xiao}}),
* M5stack - M5Stamp-C3 ((https://shop.m5stack.com/products/m5stamp-c3-mate-with-pin-headers)) (figure {{ref>esp32_stampc3}}).
{{ :en:iot-open:hardware2:esp32-c3-devkitm-1-v1-annotated-photo.png?400 | Espressif - ESP32-C3-DevkitM-1}}
A M5Stamp-C3u version with built-in JTAG interface is also available
== ESP32-C3 chip comparison ==
The Esp32-C3 as a more modern one, can successfully replace the oldest family of ESP8266 chips, so table {{ref>esp32c3}} provides a brief comparison of the essential features of the ESP8266 & ESP32-S3 systems ((https://docs.espressif.com/projects/esp-idf/en/v5.0/esp32/hw-reference/chip-series-comparison.html)).
Esp8266 & ESP32-C3 family brief comparison
\\
^**Feature**^**ESP8266**^**ESP32-C3 Series**^
|Launch year|2014|2020|
|Core|Xtensa® single core 32-bit LX6|32-bit single-core RISC-V|
|Wi-Fi protocols|802.11 b/g/, 2.4 GHz up to 72.2. Mbps|802.11 b/g/n, 2.4 GHz up to 150 Mbps|
|Bluetooth®| ✖️|Bluetooth 5.0|
|Typical frequency|80 MHz |160 MHz|
|SRAM|160kB|400 KB|
|ROM|384 KB |384 KB for booting and core functions|
|Embedded flash|✖️|4 MB or none, depending on variants|
|RTC memory|768B|8kB|
|Cache |32KB instruction|16kB|
|PMU|✔️|✔️|
|**Peripherals**| | |
|ADC|10-bit|Two 12-bit SAR ADCs, at most 6 channels|
|DAC|✖️|✖️|
|Timers|2 x 23 - bit|Two 54-bit general-purpose timers, and three watchdog timers|
|Temperature sensor|1|1|
|Touch sensor|✖️|✖️|
|Hall sensor|✖️|✖️|
|GPIO|17|22|
|SPI|2|3|
|LCD interface|✖️|✖️|
|UART|2 – One Tx only|2 |
|I2C|1- only software|1|
|I2S|1 |1, can be configured to operate with 8/16/24/32-bit resolution as an input or output channel.|
|Camera interface|✖️|✖️|
|DMA|✖️|General-purpose, 3 TX channels, 3 RX channels|
|RMT|1 x TX + 1 x RX|4 channels 2, 2 TX channels, 2 RX channels|
|Pulse counter|✖️|✖️|
|LED PWM|5 channels|6 channels|
|PWM|✖️/software 8 ch|✖️|
|TWAI® controller (compatible with ISO 11898-1)|✖️|1|
|SD/SDIO/MMC host controller|✖️|✖️|
|SDIO slave controller|✖️|✖️|
|Ethernet MAC|✖️|✖️|
|Debug Assist JTAG|✖️|1|
|**Security**| | |
|Secure boot|✖️|✔️ Faster and safer, compared with ESP32, |
|Flash encryption|✖️|✔️ Safer, compared with ESP32, XTS-AES-128|
|OTP|1024-bit|4096-bit|
|AES|✖️|✔️ AES-128, AES-256 (FIPS PUB 197); DMA support|
|HASH|SHA-1, SHA-256, SHA-384, SHA-512 (FIPS PUB 180-4)|SHA-1, SHA-224, SHA-256 (FIPS PUB 180-4); DMA support|
|RSA|Up to 4096 bits|Up to 3072 bits|
|RNG|✔️|✔️|
|HMAC|✖️|✔️|
|Digital signature|✖️|✔️|
|XTS|✖️|✔️ XTS-AES-128|
|**Other**| | |
|Light sleep |2 mA|130μA|
|Deep Sleep|20 μA|5 μA|
|Hibernation|-|-|
|Power off|0.5 μA|1μA|
|Size|QFN32 5*5|QFN32 5*5|
\\
===== ESP32-C6 =====
==ESP32-C6 General Information==
ESP32-C6 is Espressif's first WiFi 6 SoC integrating 2.4 GHz WiFi 6, Bluetooth 5.3 (Low Energy) and the 802.15.4 protocol. It is based on a high-performance (HP) 32-bit RISC-V processor, which can be clocked up to 160 MHz, and also has a low-power (LP) 32-bit RISC-V processor, which can be clocked up to 20 MHz. It has a 320KB ROM, a 512KB SRAM and works with external flash. The ESP32-C6, with its support for WiFi 6 and Bluetooth 5.3, can be a potential candidate for devices seeking to integrate into the Matter standard. Matter intends to create a universal standard for smart home devices to ensure interoperability and ease of use across different brands and ecosystems. Devices equipped with the ESP32-C6 can potentially comply with the Matter standard to ensure compatibility with other Matter-certified devices. They can be used to develop various other Matter-ecosystem solutions, such as Matter Gateways, Thread Border Routers or Zigbee Matter Bridges. However, adherence to the Matter standard involves hardware and software considerations, and manufacturers must ensure their devices meet the required protocols for certification.
== ESP32-C6 Architecture Overview ==
Figure {{ref>esp32c6_functions}} shows a functional block diagram of the ESP32 chip. Main common features of the ESP32-C6 are: ((https://www.espressif.com/sites/default/files/documentation/esp32-c6_datasheet_en.pdf))
**Processors**
* **Main processor:** 32-bit RISC-V single-core CPU up to 160MHz,
* **Cores**: 1,
* External main crystal clock,
* External 32 kHz crystal oscillator for RTC or internal RC.
* **Low-power processor:** up to 20MHz
* **Cores**: 1,
* External main crystal clock,
* External 32 kHz crystal oscillator for RTC or internal RC.
**Wireless connectivity**
* **WiFi:**(802.11ax 20MHz only non-AP mode),
* ** WiFI:**(802.11b/g/n @ 2.4 GHz up to 150 Mbit/s) with simultaneous Infrastructure BSS Station mode/SoftApp mode/Promiscuous mode,
* **Bluetooth:** v5.3 Bluetooth Low Energy (BLE) ( speed: 125 Kbps - 2 Mbps) with multiple advertisement sets,
* **IEEE 802.15.4-2015:** up to 250 kbps; Thread 1.3; ZigBee 3.0.
**Memory: Internal memory**
* **Embedded flash** 4 MB,
* **ROM:** 320 kB (booting and core functions),
* **HP SRAM:** 510 kB,
* ** LP SRAM:** 16 kB,
* **RTC fast SRAM:** 8 kB,
* ** eFuse ** - 4 Kbit - 1792 bits reserved for encryption key and device ID.
**Peripheral Input/Output**
* 30xGPIO (QFN40) or 22xGPIO (QFN32),
* General DMA controller (GDMA), with 3 transmit channels and 3 receive channels,
* 1 × I²C (Inter-Integrated Circuit),
* 2 x UART,
* 1 x Low-Power UART,
* 2 × TWAI® controller compatible with ISO 11898-1 (CAN Specification 2.0),
* 2 × SPI (Serial Peripheral Interface for flash),
* 1 × SPI (Serial Peripheral Interface universal ),
* 1 × I²S (Integrated Inter-IC Sound),
* 1 × SDIO 2.0 slave controller,
* 1 × Motor Control PWM (MCPWM),
* LED PWM up to 6 channels,
* 1 x USB Serial/JTAG controller,
* 1 x Remote control peripheral (TX/RX),
* 1 x Parallel IO interface (PARLIO),
* 1 x 12-bit SAR ADCs (analog-to-digital converter) up to 7 channels,
* 1 x temperature sensor.
**Security**
* Secure boot,
* Flash encryption,
* External Memory Encryption and Decryption (XTS_AES),
* 4096-bit OTP, up to 1792-bit for customers,
* Trusted execution environment (TEE) controller and access permission management (APM),
* Cryptographic hardware acceleration:
* AES-128/256,
* ECC,
* SHA accelerator,
* RSA accelerator,
* HASH (FIPS PUB 180-4),
* random number generator (RNG),
* digital signature.
{{ :en:iot-open:hardware2:esp32c6.png?400 | ESP32-C6 functional block diagram}}
ESP32-C6 functional block diagram
==ESP32-C6 Modules==
The following modules are currently available (table {{ref>esp32c6_modules}}):
==ESP32-C6 Development Boards==
There are not many prototype kits with ESP32-C6 SOCs on the market yet. Two sets released by the manufacturer deserve special attention. They are both entry-level development boards:
* Espressif - ESP32-C6-DevkitM-1 ((https://docs.espressif.com/projects/espressif-esp-dev-kits/en/latest/esp32c6/esp32-c6-devkitm-1/index.html))(figure {{ref>esp32_c6_devkitm}}), \\
* Espressif - ESP32-C6-DevkitC-1((https://docs.espressif.com/projects/espressif-esp-dev-kits/en/latest/esp32c6/esp32-c6-devkitc-1/index.html))(figure {{ref>esp32_c6_devkitc}}) . \\
{{ :en:iot-open:hardware2:esp32-c6-devkitm-1-pin-layout.png?400 | Espressif ESP32-C6-DEVKITM-1}}
They allow you to test all processor functions, including WiFi, Bluetooth LE, Zigbee, and Thread.
When purchasing the ESP32-C6 development board, please note that they may contain pre-production versions of ESP32-C6 that may not have full functionality implemented.